This invention relates generally to electronic circuits and, more particularly, to digital logic circuits including storage elements for storing data responsive to one or more synchronizing clock signals.
Many complex digital logic circuits, including processors, employ a technique called xe2x80x9cpipeliningxe2x80x9d to perform more operations per unit of time (i.e., to increase throughput). Pipelining involves dividing a process into sequential steps, and performing the steps sequentially in independent stages. For example, if a process can be performed via n sequential steps, a pipeline to perform the process may include n separate stages, each performing a different step of the process. Since all n stages can operate concurrently, the pipelined process can potentially operate at n times the rate of the non-pipelined process. When a number of operations to be performed is large, the sizeable delay between the time the first operation is started and the first operation is completed does not appreciably increase an average time required per operation.
Hardware pipelining involves partitioning a sequential process into stages, and adding storage elements (i.e., groups of latches or flip-flops, commonly called registers) between stages to hold intermediate results. When the number of operations to be performed is large and the cost of adding storage elements between stages is small compared to the cost of the stages themselves, pipelining is advantageous.
In general, two factors prevent a pipelined process from reaching the theoretical n-fold gain in operating rate: (i) A maximum rate at which each step of the operation can be performed will be determined by the slowest stage in the process, and (ii) a certain amount of time is required to transfer the results of one stage to the next.
In a typical hardware pipeline, combinational logic within each stage performs logic functions upon input signals received from a previous stage. The storage elements positioned between the combinational logic of each stage are responsive to one or more synchronizing clock signals.
Latches are relatively simple storage structures that, when enabled, transfer input signal values to outputs. A pipelined system may include latches positioned between the combinational logic of each stage, wherein the latches are responsive to a single clock signal. In this situation, an active time period (i.e., a xe2x80x9cwidthxe2x80x9d) of the clock signal must be long enough (i.e., xe2x80x9cwidexe2x80x9d enough) to allow every signal to propagate through a single stage of the pipeline, yet short enough (i.e., xe2x80x9cnarrowxe2x80x9d enough) to prevent any signal from propagating through more than one pipeline stage. Due to the difficulty in satisfying the above requirements under many varying operating conditions (e.g., temperature, power supply voltage, manufacturing, and aging), this xe2x80x9cnarrow pulse clockingxe2x80x9d scheme has largely been abandoned in favor of more robust schemes.
More complex approaches such as latch-pair storage elements and associated two-phase clocking schemes more readily satisfy the above timing requirements. In general, a latch-pair storage element includes two series-connected latches, each responsive to a different one of two clock signals. The two clock signals are substantially complementary, often made non-overlapping, and constitute a two-phase clocking scheme. A first or xe2x80x9cmasterxe2x80x9d latch of a latch-pair storage element xe2x80x9ccapturesxe2x80x9d data at an input in response to one of the two clock signals, and the second or xe2x80x9cslavexe2x80x9d latch xe2x80x9claunchesxe2x80x9d stored data at an output in response to the second clock signal.
In general, common complementary metal oxide semiconductor (CMOS) logic structures (e.g., gates, latches, registers, and the like) are either static or dynamic. Static logic structures generally include xe2x80x9cstaticxe2x80x9d nodes connected via one or more low resistance paths to one of two power supply voltage levels (e.g., to either VDD or VSS) at all times during operation. The low resistance paths are typically formed through activated metal oxide semiconductor (MOS) devices (i.e., transistors).
Dynamic logic structures, on the other hand, generally include xe2x80x9cdynamicxe2x80x9d nodes having capacitances upon which electrical charges are stored. The dynamic nodes are typically charged to one voltage level (i.e., precharged) during a precharge operation, and selectively charged (e.g., discharged) to another voltage level during a subsequent evaluation operation dependent upon one or more input signals. For example, dynamic nodes of dynamic logic circuits are commonly precharged to a high voltage level when a synchronizing clock signal is at one voltage level (e.g., a low voltage level), and selectively discharged to a low voltage level dependent upon the input signals when the clock signal transitions to another voltage level (e.g., a high voltage level).
In general, static logic circuits are less sensitive to noise, clock signal timing, signal race conditions, and semiconductor process variations than dynamic logic structures. Dynamic logic structures, on the other hand, typically operate faster and require less integrated circuit die areas than similar static logic structures. Due to their drawbacks, dynamic logic circuits are often relegated to highly-specialized, hand-tuned circuits, typically those along critical timing paths.
Scan testing is commonly used to test sequential logic circuits of integrated circuits. In typical scan testing approaches, some or all of the storage elements of an integrated circuit are modified to include scan inputs and outputs, and to select the scan inputs in a scan testing mode (i.e., in a scan mode). The scan inputs and outputs of the storage elements are connected together in series to form a shift register (i.e., a scan chain). In the scan mode, the storage elements are used to apply predetermined input signals (i.e., test input signals) to combinational logic (e.g., combinational logic of multiple pipeline stages). During a first shift mode operation, scan data is shifted in to each of the storage elements. The output signals produced by the storage elements are then applied to the combinational logic, and signals produced by the combinational logic are captured by the storage elements. During a second shift mode operation, the captured signals produced by the combinational logic are shifted out of the storage elements of the integrated circuit, and compared to expected values to determine if the combinational logic is performing a desired logic function.
Scan testing is typically performed at clock signal frequencies that are less than normal operating clock signal frequencies. Due to charge leakage at dynamic nodes, (faster) dynamic logic structures often do not operate properly at these lower clock frequencies, necessitating the use of (slower) static logic structures in scan storage elements.
A latching dynamic logic structure is disclosed including a static logic interface, a dynamic logic gate, and a static latch. The static logic interface receives a data signal, a select signal, and a clock signal, and produces a first intermediate signal such that when the select signal is active, the first intermediate signal is dependent upon the data signal for a period of time following a transition of the clock signal.
The dynamic logic gate receives the first intermediate signal and discharges a dynamic node following the transition of the clock signal dependent upon the first intermediate signal. The static latch receives the clock signal and is coupled to the dynamic node of the dynamic logic gate, and produces an output signal such that the output signal assumes one of two logic levels (e.g., a logic xe2x80x980xe2x80x99 level) following the transition of the clock signal, and assumes the other logic level (e.g., a logic xe2x80x981xe2x80x99 level) in the event the dynamic node is discharged.
A scan-testing-enabled version of the latching dynamic logic structure is described, as is an integrated circuit including the latching dynamic logic structure.